Sensitivity of interconnect delay to on-chip inductance

Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly simplify the extraction of on-chip inductance. The first characteristic is that the sensitivity of a signal waveform to errors in the inductance values is low, particularly the propagation delay and the rise time. It is quantitatively shown in this paper that the error in the propagation delay and rise time is below 9.4% and 5.9%, respectively, assuming a 30% relative error in the extracted inductance. If an RC model is used for the same example, the corresponding errors are 51% and 71%, respectively. The second characteristic is that the magnitude of the on-chip inductance is a slowly varying function of the width of a wire and the geometry of the surrounding wires. These two characteristics can be exploited by using simplified techniques that permit approximate and sufficiently accurate values of the on-chip inductance to be determined with high computational efficiency.